Building a Retargetable Local Instruction Scheduler

Historically, instruction schedulers have been developed in an ad hoc manner. This paper explores using one scheduler for a number of different architectures and the ramifications of this. In order to achieve this generality, a machine description that encompasses a rich set of architectural features and a scheduler than can accommodate these descriptions are needed. Using the techniques described here, an efficient local instruction scheduler that generates excellent code for instruction-level parallel architectures can be built.